1. Field of the Invention
The invention relates in general to a flat display and driving method thereof, and more particularly to a flat display structure using a voltage adapting device to input a working voltage to a gate line and driving method thereof.
2. Description of the Related Art
In a conventional large-scaled glass on array (GOA) liquid crystal display (LCD), the gate line has a high loading charge, so the gate signal is likely to be coupled with the clock signal of the driving circuit, resulting in the problems of gate signal distortion and gate delay. To resolve the coupling and distortion problems, a pull down circuit is disposed on each gate line to improve the display quality.
Referring to FIG. 1, partial structure of a conventional GOA liquid crystal display equipped with a pull down circuit is shown. The liquid crystal display 100 includes a scan driving circuit 102, a data driving circuit 104, a pixel matrix 108 consisting of a number of pixels 106, and n pull down circuits 109. The pull down circuit 109 includes N-type metal oxide semiconductor (NMOS) transistors Q1˜Qn, n is a positive integer.
When the scan driving circuit 102 sequentially outputs n gate signals S1˜Sn through n gate lines G1˜Gn to the pixels 106 on each row to turn on the thin film transistor (TFT) 106a of each pixel 106, the data driving circuit 104 outputs a data signal through m data lines L1˜Lm and charges the pixel electrode 106b of each pixel 106 through the TFT transistor 106a, so that the liquid crystal molecules are rotated to display corresponding pixel images.
Furthermore, as shown in FIG. 1, the NMOS transistors Q1˜Qn are disposed outside the pixel matrix 108. The drains of the NMOS transistors Q1 Qn are respectively coupled to the tail ends of the gate lines G1 Gn. The sources of the NMOS transistors Q1˜Qn are coupled to a low level working voltage Vee of the scan driving circuit 102. The gates of the NMOS transistor Q1˜Q(n−1) are respectively coupled to the front end of the next gate lines G2˜Gn through (n−1) transmission lines T1˜T(n−1), and the gate of the NMOS transistor Qn is coupled to the scan driving circuit 102 through the transmission line Tn. By doing so, the scan driving circuit 102 outputs the gate signal Sn to turn on the corresponding nth row pixel 106 through the gate line Gn for example; and during the next timing period, the scan driving circuit 102 turns on the NMOS transistor Qn by using the high level gate signal S(n+1) outputted by the transmission line Tn so that the gate signal Sn is promptly boosted to Vee level. The remaining gate signals S1˜S(n−1) can use the NMOS transistors Q1˜Q(n−1) to achieve the same function. Thus, the above problems of gate delay and signal distortion are resolved.
Despite the conventional liquid crystal display 100 can improve the gate delay by using the NMOS transistors Q1˜Qn, however, in terms of structure, the transmission lines T1˜Tn disposed according to the disposition of the NMOS transistors Q1˜Qn have to pass through the pixel matrix 108, significantly decreasing the aperture ratio of each pixel 106 of the pixel matrix 108. Besides, when the scale of the liquid crystal display 100 is enlarged, the accompanied loading effect will cause significant ripple effect to the gate signals S1˜Sn. However, within the display time of one frame, each of the NMOS transistors Q1˜Qn is only turned on once and is incapable of decreasing the ripples generated when the NMOS transistor is not turned on, largely affecting the display quality.